{"title": "Topographic Map Formation by Silicon Growth Cones", "book": "Advances in Neural Information Processing Systems", "page_first": 1163, "page_last": 1170, "abstract": null, "full_text": "Topographic  Map  Formation  by  Silicon \n\nGrowth  Cones \n\nBrian Taba and Kwabena Boahen \n\nDepartment of Bioengineering \n\nUniversity of Pennsylvania \n\nPhiladelphia, P A  19104 \n\n{blaba, kwabena}@neuroengineering.upenn.edu \n\nAbstract \n\nWe  describe  a  self-configuring  neuromorphic  chip  that  uses  a \nmodel of activity-dependent axon remodeling to  automatically wire \ntopographic  maps  based  solely  on  input  correlations.  Axons  are \nguided by growth cones, which are modeled in analog VLSI for the \nfirst  time.  Growth  cones  migrate  up  neurotropin  gradients,  which \nare  represented  by  charge  diffusing  in  transistor  channels.  Virtual \naxons  move  by  rerouting  address-events.  We  refined  an  initially \ngross topographic projection by simulating retinal wave input. \n\n1  Neuromorphic  Systems \n\nNeuromorphic  engineers  are  attempting  to  match  the  computational  efficiency  of \nbiological  systems  by  morphing  neurocircuitry  into  silicon  circuits  [1].  One  of the \nmost  detailed  implementations  to  date  is  the  silicon  retina  described  in  [2] .  This \nchip  comprises  thirteen different cell types,  each  of which must be individually and \npainstakingly  wired.  While  this  circuit-level  approach  has  been  very  successful  in \nsensory  systems,  it  is  less  helpful  when  modeling  largely  unelucidated  and \nexceedingly plastic higher processing centers in cortex. \n\nInstead  of  an  explicit  blueprint  for  every  cortical  area,  what  is  needed  is  a \ndevelopmental rule that can wire complex circuits from  minimal  specifications.  One \ncandidate  is  the  famous  \"cells  that  fire  together  wire  together\"  rule,  which \nstrengthens  excitatory  connections  between  coactive  presynaptic  and  postsynaptic \ncells.  We  implemented a self-rewiring scheme  of this  type in  silicon,  taking our cue \nfrom axon remodeling during development. \n\n2  Growth  Cones \n\nDuring development,  the brain wires axons into a myriad of topographic projections \nbetween  regions.  Axonal  projections  initially  organize  independent  of  neural \nactivity,  establishing  a  coarse  spatial  order  based  on  gradients  of substrate-bound \nmolecules  laid  down  by local  gene  expression.  These  gross topographic projections \nare  refined  and  maintained  by  subsequent  neuronal  spike  activity,  and  can  reroute \n\n\fpost \n\nII \n\nA \n\nB \n\nFigure  1:  A.  Postsynaptic  activity  is  transmitted  to  the  next  layer  (up  arrows)  and \nreleases  neurotropin  into  the  extracellular  medium  (down  arrows).  B.  Presynaptic \nactivity  excites  postsynaptic  dendrites  (up  arrows)  and triggers  neurotropin  uptake \nby active  growth  cones  (down  arrows).  Each growth  cone  samples  the  neurotropin \nconcentration  at  several  spatial  locations,  measuring  the  gradient  across  the  axon \nterminal.  Growth  cones  move  toward higher neurotropin  concentrations.  C.  Axons \nthat fire  at the same time migrate to the same place. \n\nthemselves  if their  signal  source  changes.  In  such  cases,  axons  abandon  obsolete \nterritory and invade more promising targets [3]. \n\nAn  axon  grows  by adding  membrane  and microtubule  segments  to  its  distal  tip,  an \namoeboid  body  called  a  growth  cone.  Growth  cones  extend  and  retract  fingers  of \ncytoplasm called filopodia,  which are sensitive to local levels of guidance chemicals \nin  the  surrounding  medium.  Candidate  guidance  chemicals  include  BDNF  and NO, \nwhose release can be triggered by action potentials in the target neuron [4]. \n\nOur  learning  rule  is  based  on  an  activity-derived  diffusive  chemical  that  guides \ngrowth  cone  migration.  In  our  model,  this  neurotropin  is  released  by  spiking \nneurons  and  diffuses  in  the  extracellular medium  until  scavenged by glia or bound \nby  growth  cones  (Figure  lA).  An  active  growth  cone  compares  amounts  of \nneurotropin  bound  to  each  of its  filopodia  in  order  to  measure  the  local  gradient \n(Figure  IB).  The growth cone then moves up the gradient, dragging the axon behind \nit.  Since  neurotropin  is  released  by  postsynaptic  activity  and  axon  migration  is \ndriven by presynaptic  activity,  this  rule  translates temporal  coincidence  into  spatial \ncoincidence (Figure  1 C). \n\nFor topographic map formation,  this migration rule requires temporal correlations in \nthe presynaptic plane to reflect neighborhood relations. We supply such correlations \nby  simulating  retinal  waves,  spontaneous  bursts  of  action  potentials  that  sweep \nacross  the  ganglion  cell  layer  in  the  developing  mammalian  retina.  Retinal  waves \nstart  at  random  locations  and  spread  over  a  limited  domain  before  fading  away, \neventually tiling the  entire retinal plane  [5].  Axons participating in the  same retinal \n\n\f~ , , , \n\n\\ , , \n\nj=~==~~~~~~~~~\u00b7VG~' \n, \n\nA \n\nVGCK \n\nNK \n\n>-\n> \nu a: \n\n... \n\nB \n\nXmit X \n\niJC \n\n>-\n-'-' \nE \nx \n\nFigure  2:  A.  Chip block diagram.  Axon  terminal  (AT)  and neuron (N)  circuits  are \narrayed hexagonally,  surrounded by a continuous charge-diffusing lattice. An active \naxon  terminal  (AT x,y)  excites  the  three  adjacent  neurons  and  its  growth  cone \nsamples  neurotropin  from  four  adjacent  lattice  nodes.  The  growth  cone  sends  the \nmeasured  gradient  direction  off-chip  (VGCx,y)'  An  active  postsynaptic  neuron \n(Nx,y)  releases neurotropin into the six surrounding lattice nodes and sends its spike \noff-chip.  B.  System  block  diagram.  Presynaptic  neurons  send spikes  to  the  lookup \ntable  (LUT),  which  routes  them  to  axon  terminal  coordinates  (AT)  on-chip.  Chip \noutput filters  through  a microcontroller (f.lC)  that translates  gradient measurements \n(VGC)  into  LUT updates  (ilAT).  Postsynaptic  activity  (N)  may  be  returned  to  the \nLUT as  recurrent excitation and also passed on to  the next stage of the system. \n\nwave  migrate \nsince  neurotropin \nconcentration  is  maximized  when  every  cell  that  fires  at  the  same  time  releases \nneurotropin at the same place. \n\nthe  same  postsynaptic  neighborhood, \n\nto \n\nTo  prevent  all  of the  axons  from  collapsing  onto  a  single  postsynaptic  target,  we \nenforce  a  strictly  constant  synaptic  density.  We  have  a  fixed  number  of synaptic \nsites,  each  of which  can be  occupied by  one  and  only  one  presynaptic  afferent.  An \naxon terminal moves  from  one  synaptic  site to  another by swapping places with the \naxon  already  occupying  the  desired  location.  Learning  occurs  only  in  the  point-to(cid:173)\npoint wiring diagram; synaptic weights are identical and unchanging. \n\n3  System  Architecture \n\nWe  have fabricated and tested a first-generation neurotropin chip, Neurotrope 1,  that \nimplements retrograde  transmission  of a  diffusive  factor  from  postsynaptic neurons \nto  presynaptic  afferents  (Figure  2A).  The  11.5  mm2  chip  was  fabricated  through \nMOSIS  using  the  TSMC  0.35f.lm  process,  and  includes  a  40  x  20  array  of growth \ncones  interleaved with  a  20  x 20  array  of neurons.  The  chip  receives  and  transmits \n\n\f1-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\n-\n\nVdd \n\nVdd \n\nVdd \n\nVdd  : \n\n-4  M11 : \n\nVi release \n\nI \n\n-------------------------------------, \n\nVdd \n\nVdd \n\n: M12  r-\n\n-samp eO \n\n: \n\n-:- Viuptake \n\nM1 \n\nJL' \n\nFigure  3:  Neurotropin  circuit  diagram.  Postsynaptic  activity  gates  neurotropin \nrelease (left box) and presynaptic activity gates neurotropin uptake (right box). \n\nspike  coordinates  encoded  as  address-events,  permitting  ready  interface  with  other \nspike-based  chips  that  obey  this  standard  [6].  Virtual  wiring  [7]  is  realized  with  a \nlook-up table (LUT)  stored in  a separate content-addressable memory (CAM) that is \ncontrolled by an  Ubi com SX52 microcontroller (Figure 2B). \n\nThe core of the chip consists of an  array of axon terminals that target a second array \nof neurons,  all  surrounded  by  a  monolithic  pFET  channel  laid  out  as  a  hexagonal \nlattice,  representing  a  two-dimensional  extracellular  medium.  An  activated  axon \nterminal  generates  postsynaptic  potentials  in  all  the  fixed-radius  dendritic  arbors \nthat  span  its  location,  as  modeled  by  a  diffusor  network  [8].  Once  the  membrane \npotential  crosses  a  threshold,  the  neuron  fires,  transmitting  its  coordinates  off-chip \nand  simultaneously  releasing  neurotropin,  represented  as  charge  spreading  within \nthe  lattice.  N eurotropin  diffuses  spatially  until  removed  by  either  an  activity(cid:173)\nindependent leak current or an active axon terminal. \n\nAn  axon  terminal  senses  the  local  extracellular  neurotropin  gradient  by  draining \ncharge  from  its  own  node  on  the  hexagonal  lattice  and  from  the  three  immediately \nadjacent  nodes.  Charge  from  the  four  locations  is  integrated  on  independent \ncapacitors,  which  race  to  cross  threshold  first.  The  winner  of  this  latency \ncompetition  transmits  a  set  of coordinates  that  uniquely  identify  the  location  and \ndirection  of the  measured  gradient.  We  use  the  neuron  circuit  described  in  [9]  to \nintegrate neurotropin as well as dendritic potentials. \n\nCoordinates transmitted off-chip thus fall  into two categories: neuron spikes that are \nrouted  through  the  LUT,  and  gradient  directions  that  are  used  to  update  entries  in \nthe  LUT.  An  axon  migrates  simply  by  looking  up  the  entry  in  the  table \ncorresponding to  the  site  it wants  to  occupy and  swapping  that address  with that of \nits  current  location.  Subsequent  spikes  are  routed  to  the  new  coordinates.  Thus, \nalthough  the  physical  axon  terminal  circuits  are  immobilized in  silicon,  the  virtual \naxons are free to move within the postsynaptic plane. \n\n3.1  Neurotropin  circuit \n\nNeurotropin  in  the  extracellular  medium  is  represented by  charge  in  the  hexagonal \ncharge-diffusing  lattice  Ml  (Figure  3).  VCDL  sets  the  maximum  amount  of charge \nMI  can  hold.  The  total  charge  in  Ml  is  determined  by  circuits  that  implement \n\n\f11 \n\n12 \n\n13 \n\n10 \n\n, \n\nVm  - sp \n\nC1* \n\nVm  - sp \n\nC2* \n\n1 \n- s031 \n\nVm  - sp \n\nC3* \n\nFigure  4:  Latency  competition  circuit  diagram.  A  growth  cone \nintegrates \nneurotropin  samples  from  its  own  location  (right  box)  and  the  three  neighboring \nlocations  (left three  boxes).  The  first  location  to  accumulate  a  threshold  of charge \nresets its three competitors and signals its identity off-chip. \n\nactivity-dependent  neurotropin  release  and  uptake.  In  addition,  MIl  and  M12 \nprovide a path for activity-independent release and uptake. \n\nPostsynaptic  activity  triggers  neurotropin  release,  as  implemented  by the  circuit  in \nthe  left  box  of Figure  3.  Spikes  from  any  of the  three  neighboring  postsynaptic \nneurons  pull  Cspost  to  ground,  opening  M7  and  discharging  C/post  through  M4  and \nM5.  As  C/post  falls,  M6  opens,  establishing  a  transient  path  from  Vdd  to  M1  that \ninjects  charge  into  the  hexagonal  lattice.  Upon  termination  of  the  postsynaptic \nspike,  Cspost  and  C/post  are  recharged  by  decay  currents  through  M2  and  M3.  Vppost \nand  V/postout  are  chosen  such  that  Cspost  relaxes  faster  than  C/post.  permitting  C/post  to \nintegrate  several  postsynaptic  spikes  and  facilitate  charge  injection  if spikes  arrive \nin  a  burst  rather  than  singly.  V/postin  determines  the  contribution  of an  individual \nspike to the facilitation capacitor C/post . \nPresynaptic  activity  triggers  neurotropin  uptake,  as  implemented  by  the  circuit  in \nthe  right  box  of  Figure  3.  Charge  is  removed  from  the  hexagonal  lattice  by  a \nfacilitation  circuit  similar to  that used  for postsynaptic  release.  A  presynaptic  spike \ntargeted to the axon terminal pulls  C spre  to ground through M24. C spre.  in turn,  drains \ncharge  from  C/pre  through  M21  and  M22.  C/pre  removes  charge  from  the  hexagonal \nlattice through M14,  up  to  a limit set by M13, which prevents the  hexagonal  lattice \nfrom  being completely drained in  order to  avoid charge trapping. Current from  M14 \nis  divided between  five  possible  sinks.  Depending  on  presynaptic  activation,  up  to \nfour  axon  terminals  may  sample  a  fraction  of this  current  through  M 15-18;  the \nremainder is shunted to ground through M 19  in order to prevent a single presynaptic \nevent  from  exerting  undue  influence  on  gradient  measurements.  The  current \nsampled by the  axon  terminal  at  its  own  site  is  gated by  ~sampleo, which  is  pulled \nlow  by  a  presynaptic  spike  through  M26  and  subsequently  recovers  through  M25. \nIdentical  circuits  in  the  other  axon  terminals  generate  signals  ~sample], ~sample2' \nand  ~sample3. Sample  currents  la,  h  hand 13  are  routed  to  latency  competition \ncircuits in the four adjacent axon terminals. \n\n\fFigure 5:  Retinal  stimulus  and  cortical attractor.  A.  Randomly centered patches of \nactive  retinal  cells  (left)  excite  cortical  targets  (right).  B.  Density  plot  of a  single \nmobile  growth  cone  initialized  in  a  static  topographic  projection.  Histograms  bin \ncolumn (0'=3.27) and row (0'=3.79) coordinates observed (n=800). \n\n3.2  Latency  competition  circuit \n\nEach  axon  terminal  measures  the  local  neurotropin  gradient by sampling a  fraction \nof the  neurotropin  present  at  its  own  site,  location  0,  and  the  three  immediately \nadjacent  nodes  on  the  hexagonal  lattice,  locations  1-3.  Charge  drained  from  the \nhexagonal  lattice  at  these  four  sites  is  integrated  on  a  separate  capacitor  for  each \nlocation.  The  first  capacitor  to  reach  the  threshold  voltage  wins  the  race,  resetting \nitself and all of its competitors and signaling its victory off-chip. \n\nIn the  circuit that samples neurotropin from  location  1 (left box of Figure 4), charge \npulses 1J  arrive  through  diode  Ml  and  accumulate  on  capacitor  CJ in  an  integrate(cid:173)\nand-fire  circuit  described  in  [9].  Upon  crossing  threshold  this  circuit  transmits  a \nswap request  ~sol, resets  its  three  competitors by using M6  to pull the  shared reset \nline  GRST high,  and  disables  M4  to  prevent  GRST from  using  M3  to  reset  CJ \u2022  The \nswap  request  ~sol remains  low  until  acknowledged  by  sil,  which  discharges  CJ \nthrough M2.  During the time that ~sol is  low,  the other three capacitors are shunted \nto  ground  by  GRST,  preventing  late  arrivals  from  corrupting  the  declared  gradient \nmeasurement before  it  has  been  transmitted  off-chip.  C]  being  reset releases  GRST \nto  relax to  ground through M24 with a decay time determined by Vgrst\u2022 \n\nC]  is  also  reset  if the  neighboring  axon terminal  initiates  a  swap.  GRSTil  is  pulled \nlow  if either  the  axon  terminal  at  location  1  decides  to  move  to  location  0  or  the \naxon  terminal  at  location  0  decides  to  move  to  location  1.  The  accumulated \nneurotropin  samples  at both  locations  become  obsolete  after  the  exchange,  and  are \ntherefore discarded when GRST is pulled high through MS.  Identical circuits sample \nneurotropin from locations 2 and 3 (center two boxes of Figure 4). \n\nIf Co  (right box of Figure 4) wins the latency competition, the axon terminal decides \nthat  its  current location  is  optimal  and  therefore  no  action  is  required.  In  this  case, \nno  off-chip  communication  occurs  and  Co  immediately  resets  itself and  its  three \nrivals.  Thus,  the  location  0  circuit is  identical  to  those  of locations  1-3  except that \nthe  inverted  spike  is  fed  directly  back  to  the  reset  transistor  M20  instead  of to  a \ncommunication  circuit.  Also,  there  is  no  GRSTiO  transistor  since  there  is  no  swap \npartner. \n\n4  Results \n\nWe  drove  the  chip  with  a  sequence  of randomly  centered  patches  of presynaptic \nactivity  meant  to  simulate  retinal  waves.  Each  patch  consisted  of  19  adjacent \npresynaptic cells:  a randomly  selected presynaptic cell and its  nearest,  next-nearest, \n\n\fPostsynapti c \n\n~ . '~.~'~ .. \n\n+ 12000 patches \n\n20 .0 \n\n0 \u00b7 .. \"\"  ~~ \n\nIII  17 .5 \n\n2 \n(jj \n\n15 .0 \n\nC \n<0 \n\n~  7.5 \n5.0 \n2.5 \n\nPresynaptic \n\n+.J \nc \n~ \nQ) \nc \n= Q) \n\ncL \n\nc \n0 \n. .0 \n\\'t \n<0 \n1) \ncL \n\nA \n\n~o \n0--------1. 0 \n~o \n0--------1. 0 \n~. \n\n.-... \n\n~<:i \n~t:J \n\nB \n\nC \n\n2k  4k  6k  8k  10k  12k \n\nNumber of  patches \n\nFigure  6:  Topographic  map  evolution.  A.  Initial  maps.  Axon  terminals  in  the \npostsynaptic plane (right) are dyed according to  the presynaptic coordinates of their \ncell  body  (left).  Top  row:  Coarse  initial  map.  Bottom row:  Perfect  initial  map.  B. \nPostsynaptic plane after 12000 patch presentations. C. Map error in units of average \npostsynaptic  distance  between  axon  terminals  of presynaptic  neighbors.  Top  line: \nrefinement of coarse initial map; bottom line: relaxation of perfect initial map. \n\nand  third-nearest  presynaptic  neighbors  on  a  hexagonal  grid  (Figure  5A).  Every \npatch  participant  generated  a  burst  of  8192  spikes,  which  were  routed  to  the \nappropriate  axon  terminal  circuit  according  to  the  connectivity  map  stored  in  the \nCAM.  About 100 patches were presented per minute. \n\nTo  establish an  upper performance bound, we initialized the  system with a perfectly \ntopographic projection and  generated bursts  from the  same retinal patch, holding all \ngrowth cones  static except for the one projected from the  center of the patch, which \nwas  free  to  move  over  the  entire  cortical  plane.  Over  800  min,  the  single  mobile \ngrowth  cone wandered within  the  cortical area of the  patch  (Figure  5B),  suggesting \nthat the patch radius limits maximum sustainable topography even in the ideal case. \n\nTo  test  this  limit  empirically,  we  generated  an  initial  connectivity  map  by  starting \nwith  a  perfectly  topographic  projection  and  executing  a  sequence  of (N/2)2  swaps \nbetween  a  randomly  chosen  axon  terminal  and  one  of  its  randomly  chosen \npostsynaptic neighbors, where N  is the number of axon terminals used.  We opted for \na  fanout  of 1 and  full  synaptic  site  occupancy,  so  480  presynaptic  cells  projected \naxons  to  480  synaptic  sites.  (One  side  of  the  neuron  array  exhibited  enhanced \nexcitability,  apparently due  to  noise  on the power rails,  so  the  320 synaptic sites  on \nthat side were abandoned.) The perturbed connectivity map preserved a loose global \nbias,  representing  the  formation  of a  coarse  topographic  projection  from  activity(cid:173)\nindependent cues.  This new initial map was then allowed to  evolve according to  the \nswap  requests  generated by the  chip.  After  approximately  12000  patches,  a  refined \ntopographic projection reemerged (Figure 6A,B). \n\nTo  investigate  the  dynamics  of topographic  refinement,  we  defined  the  error  for  a \nsingle  presynaptic  cell  to  be  the  average  of the  postsynaptic  distances  between  the \naxon  terminals  projected  by  the  cell  body  and  its  three  immediate  presynaptic \nneighbors.  A  cell  in  a  perfectly  topographic  projection  would  therefore  have  unit \nerror.  The  error  drops  quickly  at  the  beginning of the  evolution as  local  clumps  of \ncorrelated axon terminals crystallize.  Further refinement requires the  disassembly of \nlocally  topographic  crystals  that  happened  to  nucleate  in  a  globally  inconvenient \nlocation.  During  this  later  phase,  the  error  decreases  slowly  toward  an  asymptote. \nTo  evaluate this limit we seeded the system with a perfect projection and let it relax \n\n\fto  a sustainable degree  of topography,  which we  found  to have  an  error of about  10 \nunits (Figure 6C). \n\n5  Discussion \n\nOur  results  demonstrate  the  feasibility  of  a  spike-based  neuromorphic  learning \nsystem based on principles of developmental plasticity.  This neurotropin chip  lends \nitself readily to  more  ambitious  multichip  systems  incorporating silicon  retinae that \ncould  be  used  to  automatically  wire  ocular  dominance  columns  and  orientation(cid:173)\nselectivity  maps  when  driven  by  spatiotemporal  correlations  among  neurons  of \ndifferent origin (e.g.  left eye/right eye) or type (ON/OFF). \n\nA  related  model  of  chemical-driven  developmental  plasticity  posits  an  activity(cid:173)\ndependent competition for  a local  sustenance factor,  or neurotrophin.  Axon weights \nsaturate  at  neurotrophin-rich  locations and vanish  at neurotrophin-starved locations, \npruning a dense initial arbor until only the final  circuit remains  [10].  By contrast,  in \nour chemotaxis model,  a handful of growth cone-guided wires rearrange themselves \nby  moving  through  locations  at  which  they  had  no  initial  presence.  These  two \nmechanisms  could  plausibly  complement  each  other:  noisy  gradient  measurements \nestablish  an  initial  axonal  arbor  that  can  then  be  pruned  to  eliminate  outliers  and \nrefine local topography.  We can use a similar approach to  improve our silicon maps. \n\nAcknowledgments \n\nWe  would  like  to  thank  K.  Hynna  and  K.  Zaghloul  for  assistance  with  fabrication \nand  testing.  This  project  was  funded  in  part  by  the  David  and  Lucille  Packard \nFoundation  and the  NSF/BITS  program  (EIA0130822).  B.T.  received support from \nthe Dolores Zohrab Liebmann Foundation. \n\nReferences \n\n[1]  C.  Mead (1990) Neuromorphic electronic systems. IEEE Proc,  78(10):  1629-1636. \n\n[2]  K.A. Zagh1ou1  (2002) A  silicon implementation of a novel model for  retinal processing. \n\nPhD thesis, University of Pennsylvania. \n\n[3]  M.  Sur  and  C.A.  Leamy  (2001)  Development  and  plasticity  of  cortical  areas  and \n\nnetworks. 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Boahen  (2001)  Arbitrated  address  event \nrepresentation digital image sensor. IEEE International Solid State  Circuits  Conference, \npp 92-93. \n\n[10] T.  Elliott  and  N.R.  Shadbolt  (1999)  A  neurotrophic  model  of the  development  of the \nretinogeniculocortical  pathway  induced  by  spontaneous  retinal  waves.  J  Neurosci, \n19:7951-7970. \n\n\f", "award": [], "sourceid": 2211, "authors": [{"given_name": "Brian", "family_name": "Taba", "institution": null}, {"given_name": "Kwabena", "family_name": "Boahen", "institution": null}]}